Pull-up resistor and logic-net workflow
A pull-up value that works statically can still be too slow, too hot, or outside the receiving logic or protocol timing rules. The workflow has to cover current, thresholds, capacitance, and power together.
Reviewed 4 July 2026
Quick answer
How should you size a pull-up resistor on a logic net?
Start from the pull-up voltage, the guaranteed logic-low or sink-current limit of the pulling device, then choose a resistor that also meets rise-time and power expectations once net capacitance and the real logic context are included.
Model summary
First-pass model summary
Use these equations, assumptions, and variables as the shared model behind the guide before moving to the worked example and linked calculators.
Minimum value to satisfy the logic-low voltage and sink-current limit.
First-pass 10%-90% rise time estimate for the pull-up RC network.
Variables and natural units
These symbols match the guide equations and use the same engineering-unit conventions as the linked calculators.
Rmin: Minimum resistance
Unit: Ω
Smallest pull-up value that keeps I_sink within device limits and V_out below V_OL.
VPU: Pull-up supply
Unit: V
Voltage rail connected through the pull-up resistor to the open-drain net.
VOL: Logic low output voltage
Unit: V
Maximum guaranteed low-level output voltage of the pulling device.
Isink: Sink current
Unit: A
Maximum current the pulling device can sink while maintaining V_OL.
tr: Rise time
Unit: s
10%-90% signal rise time set by pull-up resistance and net capacitance.
Cnet: Net capacitance
Unit: F
Total capacitance on the pulled node including PCB trace, connector, and input capacitances.
Model boundary
- Sink-current limit gives a minimum resistance: R ≥ (Vpullup − Vol(max)) / Isink(max).
- Low-level voltage and leakage still need checking after the nominal resistor is chosen.
- Rise-time behaviour is a separate RC estimate from pull-up resistance and total line or input capacitance.
- Low-state resistor power is usually small but should still be checked in hot or always-on designs.
- The workflow assumes an open-drain, open-collector, or otherwise current-sinking output stage. Totem-pole outputs follow different design rules because they actively drive both high and low.
- Sleep leakage, powered-down devices, and clamp structures can matter as much as active sink current on low-power logic nets.
Worked example
3.3 V pull-up for a 3 mA maximum sink device
This example finds the minimum pull-up resistance, then checks low-state current and estimated rise time with a chosen value.
Inputs
- VCC
- 3.3 V
- VOL,max
- 0.4 V low-state ceiling
- Isink,max
- 3 mA maximum sink current
- Cnet
- 100 pF estimated net capacitance
Equation and substitution
Minimum pull-up
Rmin = 967 Ω
Chosen value
4.7 kΩ (standard E24)
Low-state current
Ilow = 0.617 mA
Rise time (100 pF)
tr ≈ 1.03 µs
Calculator workflow
Work through these calculators in order for a complete first-pass check.
-
Step 1
Pull-up resistor calculator
Choose resistance from pull-up voltage, sink current, and low-level voltage.
Open calculator -
Step 2
RC time constant calculator
Estimate how resistance and capacitance affect the pull-up transition speed.
Open calculator -
Step 3
Resistor power calculator
Check low-state dissipation and package margin where relevant.
Open calculator -
Step 4
Ohm's Law calculator
Sanity-check current, voltage drop, or a supporting interface value.
Open calculator -
Step 5
Engineering conversions calculator
Convert capacitance, time, current, or readable engineering notation as needed.
Open calculator
Guide sections
Logic thresholds come before convenience values
Choose the resistor from the guaranteed low-level voltage and sink-current capability of the pulling device, not from a habit such as always using 10kΩ. A resistor that is easy on static current but misses the logic-low or timing requirement is still the wrong value.
When timing rules override the estimate
Protocol buses, reset supervisors, and fast logic nets often define rise-time or threshold behaviour more tightly than the simple RC calculation suggests. When that happens, the device or protocol datasheet wins over the generic pull-up estimate.
Pull-up current in sleep modes
On an always-high net, the pull-up resistor does not normally dissipate power because almost no current flows. However, leakage paths through powered-down ICs, ESD structures, wet connectors, or long cables can create a meaningful DC load that shifts the logic-high level or drains a battery in sleep mode.
High pull-up values are attractive for low-power states, but they also convert tiny leakage currents into real voltage error. For example, 1 µA of leakage through a 100 kΩ pull-up creates a 0.1 V drop, which can matter on low-voltage logic families.
Open-drain vs totem-pole logic
Open-drain and open-collector outputs need an external resistor to define the high state because the device only pulls low. Totem-pole outputs actively drive both high and low, so adding a pull-up can create unwanted current paths or contention if another driver also drives the node.
Before applying a pull-up workflow, confirm that the pin is genuinely intended for open-drain, open-collector, wired-AND, reset, interrupt, or similar operation. The correct circuit for an actively driven digital output is often no pull-up at all.
Common mistakes
- Picking a default value without checking the device sink-current limit or logic-low requirement.
- Checking static DC behaviour but not line capacitance or transition time.
- Assuming one RC estimate proves compliance with a bus or interface timing specification.
When the model breaks down
- The RC estimate is first-pass only and does not replace protocol timing definitions, edge-shape limits, or detailed receiver behaviour.
- Leakage, ESD structures, powered-down devices, and multi-drop topology can change the effective pull-up requirement.
Further checks and references
- Use the pulling device and receiver datasheets for guaranteed low-level voltage, leakage, threshold, and temperature limits.
- Include wiring, connector, probe, and multi-drop capacitance before treating the RC estimate as representative.
- If the net belongs to a defined protocol, compare against that protocol timing requirement rather than relying on the calculator alone.
Related calculators
FAQ
What is the minimum safe pull-up resistance?
R ≥ (Vpullup − Vol(max)) / Isink(max), where Vol is the guaranteed low-level output voltage and Isink is the device's maximum rated sink current. Going below this risks exceeding the device's rated current and failing the logic-low voltage spec.
Does a 10 kΩ pull-up always work for I²C?
Not always. I²C specifies a maximum rise time that depends on bus capacitance. A 10 kΩ pull-up on a high-capacitance bus can be too slow. Use the RC time constant calculator to check the rise time before assuming a default value.
Should rise time be checked separately from resistance?
Yes. Static resistance sizing ensures the logic-low voltage and current requirements are met. Rise time depends on both pull-up resistance and total net capacitance and must be checked separately using the RC time constant estimate.