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Propagation Delay Calculator

Estimate one-way propagation delay, delay per millimetre, delay per inch, signal velocity, velocity factor, and effective Er from microstrip or stripline geometry.

Interconnect and velocity model

Estimate one-way propagation delay from physical length and signal velocity.

Solve for

Calculate effective Er, velocity factor, and delay from laminate Dk (Er), external trace width, and dielectric height.

Interconnect length (m)
Propagation delay (s)Output
Unit: s

Tolerance range: 524.7p to 642p s

Laminate Dk (Er) ()
Trace width (m)
Dielectric height H (m)

Propagation delay is length divided by signal velocity. The calculator derives effective Er, velocity factor, and velocity from laminate Dk (Er) and trace geometry.

Delay and velocity results

Velocity factor 0.5732.

Propagation delay581.9psRange: 524.7p to 642p s
Interconnect length100mmRange: 95m to 105m m
Delay per millimetre5.819ps/mmRange: 5.523p to 6.115p s/mm
Delay per inch147.8ps/inRange: 140.3p to 155.3p s/in
Propagation velocity171.8Mm/sRange: 163.5M to 181.1M m/s
Velocity factor0.5732x cRange: 545.52m to 603.99m x c
Effective dielectric constant3.044Range: 2.7412 to 3.3603
Laminate Dk (Er)4.2Range: 3.78 to 4.62
W/H ratio1Range: 818.18m to 1.2222

Propagation delay converts physical length and signal velocity into one-way flight time. Use microstrip or stripline geometry for timing budgets, skew intuition, and quick PCB delay estimates before detailed signal-integrity work.

PCB trace timing

Estimate delay from microstrip or stripline geometry, then review the calculated effective Er.

Derived velocity factor

Calculate velocity factor from the derived effective Er instead of entering it as a separate guessed input.

Skew budgeting

Convert length mismatch into picoseconds or nanoseconds before comparing against interface timing margin.

Solve propagation delay, length, laminate Dk (Er), trace width, or dielectric height from the remaining values. Microstrip mode uses one dielectric height H. Stripline mode records top and bottom dielectric heights H1 and H2 for stackup context; in this homogeneous delay model, those heights do not determine propagation velocity. Inputs support tolerance ranges and engineering notation such as 100m for 100mm, 150u for 150um, and 577p for 577ps.

Solve target

Timing or geometry

Use the solve selector for delay, length, laminate Dk (Er), trace width, or dielectric height, then enter the other four values.

Trace model

Microstrip or stripline geometry

Use microstrip geometry for external PCB traces, or stripline geometry with separate top and bottom dielectric heights for internal routing between reference planes.

The calculator treats velocity as constant along the entered one-way length. Geometry mode derives a first-pass effective dielectric constant, then derives velocity factor and propagation delay from that value.

Core equations

Propagation delay model

Delay from length and velocity
tdelay=lv

One-way delay is physical length divided by propagation velocity.

Velocity factor
v=VF×c

Velocity factor expresses signal speed relative to free-space light speed.

Effective dielectric estimate
v=cereff

A common first-pass relationship for PCB or dielectric-loaded paths.

Microstrip effective dielectric
ereffDk+12+Dk-12×11+12HW

First-pass external trace estimate from laminate Dk, trace width W, and dielectric height H.

Variables and natural units

l: Interconnect length

Unit: m

The one-way physical trace, cable, or interconnect length.

v: Propagation velocity

Unit: m/s

The signal velocity used for the delay estimate.

VF: Velocity factor

Unit: ratio

Velocity divided by free-space light speed.

er_eff: Effective dielectric constant

Unit: ratio

The field-weighted dielectric value seen by the signal path.

Dk: Laminate Dk (Er)

Unit: ratio

The bulk PCB material dielectric constant used by the microstrip and stripline modes.

W/H: Microstrip width-height ratio

Unit: ratio

External trace width divided by dielectric height above the reference plane.

H1, H2: Stripline dielectric heights

Unit: m

The dielectric thickness above and below an internal stripline trace.

Model boundary

Use this as a timing-budget estimate. It does not calculate controlled impedance, dispersion, via delay, connector discontinuities, solder-mask loading, copper-thickness correction, or detailed field-solver geometry.

Effective dielectric constant is not the same thing as laminate Dk. It is the field-weighted value seen by the signal path, so microstrip geometry, solder mask, stackup, and frequency can all change it.

The stripline mode assumes a homogeneous dielectric between reference planes and records separate top and bottom dielectric heights. Under the TEM delay assumption, propagation delay follows laminate Dk; trace width and plane spacing mainly affect impedance, not velocity.

This example estimates one-way delay for a 100mm external PCB trace from laminate Dk (Er) and microstrip geometry.

Worked example

100mm microstrip delay

The example uses microstrip geometry mode, so effective Er and velocity factor are calculated from laminate Dk (Er), trace width, and dielectric height.

Inputs

Timing question
What is the approximate one-way delay of a 100mm external trace with laminate Dk (Er) 4.2, width 150um, and dielectric height 150um?
Length
100mm
Geometry
Laminate Dk (Er) 4.2, W = 150um, H = 150um

Equation and substitution

ereff3.044
tdelay=0.1m172Mm/s582ps

Effective Er

3.044, derived from the first-pass microstrip geometry.

Velocity factor

About 0.573 times free-space light speed.

One-way delay

582ps, or about 0.582ns.

Next check

Compare the delay spread with setup, hold, skew, jitter, and receiver margin.

Propagation delay is usually one part of a larger timing and signal-integrity budget.

Effective dielectric is derived

Microstrip and stripline do not necessarily use the same value, and the effective value can differ from laminate Dk.

Delay is not the whole timing budget

Include driver delay, receiver thresholds, package delay, connector delay, jitter, setup, hold, and clock uncertainty.

Real interconnects are not uniform

Vias, connectors, layer changes, reference-plane gaps, solder mask, and cable construction can shift delay.

Design follow-up

Next engineering checks

Use these follow-up checks before turning the calculated value into a component choice, layout decision, or production limit.

Use these tools when the next step is frequency conversion, edge-bandwidth context, coupled-routing checks, or notation cleanup.