555 Timer Calculator
Calculate classic 555 astable oscillator timing and monostable one-shot pulse width from resistor and capacitor values.
Mode and timing parts
Calculate classic 555 astable oscillator frequency, duty cycle, and monostable one-shot pulse width.
Astable mode repeatedly charges and discharges the timing capacitor through R1 and R2, producing a free-running output waveform.
Nominal results and guaranteed range
These are idealised bipolar/CMOS 555 equations. They do not model control-voltage modulation, output-stage limits, capacitor leakage, resistor leakage, threshold tolerances, supply-voltage effects, trigger behaviour, reset timing, or device-family differences.
Calculate classic 555 astable and monostable timing
The 555 timer is still useful for quick blinkers, rough clocks, one-shot pulses, and concept work. These calculations use the classic idealised timing equations so they are best treated as first-pass estimates.
Astable oscillator
Use R1, R2, and C to estimate free-running frequency, period, high time, low time, and duty cycle.
Monostable one-shot
Use one resistor and one capacitor to estimate the output pulse width after a trigger event.
Tolerance matters
Timing capacitors often have wide tolerance and leakage, so calculate a range rather than trusting only the nominal result.
Worked example
With R1 = 10 kohm, R2 = 100 kohm, and C = 1 uF, the astable frequency is about 6.86 Hz and the period is about 146 ms. The duty cycle is about 52.4%.
Astable equation
f = 1.44 / ((R1 + 2 x R2) x C).
Duty cycle = (R1 + R2) / (R1 + 2 x R2).
The output is high while the capacitor charges through R1 and R2, and low while it discharges through R2.
Monostable equation
Pulse width = 1.1 x R x C.
A trigger event starts one timing interval, then the output returns to its stable state after the capacitor reaches the threshold.
Common mistakes and limits
Expecting exact timing
Real timing depends on capacitor tolerance, leakage, resistor tolerance, threshold variation, and device family.
Ignoring output and discharge limits
The discharge transistor and output stage have voltage and current limits that are not captured by the timing equations.
Assuming perfect 50% duty cycle
The classic astable topology has duty cycle above 50% unless additional steering diodes or alternate circuits are used.
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Engineering reference
Equations, assumptions, and design guidance
Calculates idealised 555 timer astable oscillator frequency, period, duty cycle, and monostable one-shot pulse width.
Equations and variables
f = 1.44 / ((R1 + 2*R2) * C)D = (R1 + R2) / (R1 + 2*R2)t = 1.1 * R * C- R1
- Astable charge resistor (ohm)
- R2
- Astable charge/discharge resistor (ohm)
- R
- Monostable timing resistor (ohm)
- C
- Timing capacitance (F)
Assumptions and limitations
Assumptions
- The formulas are the classic idealised 555 timer relationships.
- The timing capacitor charges and discharges between the nominal 555 threshold levels.
Limitations
- Device-family differences, threshold tolerance, supply voltage, output loading, capacitor leakage, resistor leakage, discharge transistor saturation, trigger behaviour, reset timing, and control-voltage modulation are not modelled.
Worked example and design use
Astable blinker
Inputs: R1 = 10 kohm, R2 = 100 kohm, C = 1 uF
Outputs: frequency ≈ 6.86 Hz, period ≈ 146 ms, duty cycle ≈ 52.4%
Design guidance
- Use astable mode for blinkers, clocks, tones, and rough PWM-style timing.
- Use monostable mode for one-shot pulses and trigger-stretched events.